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First, some background: Under Dodd-Frank, the CFTC was given the task of regulating the $300 trillion market for swaps in the U.S. The basic point was to bring light to a dark market and prevent another AIG by pushing as much of the over-the-counter swaps market as possible onto exchanges where prices and volume are posted. With about 80 percent of those swaps rules written,according to CFTC Chairman Gary Gensler, and a bunch of them now in effect, traders have begun “futurizing their swaps”—that is, trading futures contracts instead of entering into swaps deals. Some say that’s a clever way around Dodd-Frank. Others see it as merely a natural evolution of financial instruments.
Whatever the reason, it’s happening. And as arcane as the details may be, the potential consequences are enormous, as evidenced by Thursday’s packed house. The general consensus of those present was that Thursday was the most crowded CFTC hearing in recent memory. Lawyers and lobbyists lined the walls; congressional staffers and industry suits packed the chairs. More than 150 people crammed into the CFTC’s main conference room, and a healthy number of folks watched on TVs in the hallway outside.
Dodd-Frank has upended the derivatives market, and in the shakeout that follows, there will be winners and losers. Perhaps those with the most at stake areIntercontinentalExchange (ICE) and the Chicago Mercantile Exchange (CME), the two biggest futures exchanges in the U.S. As more companies and traders start favoring futures over swaps, the two exchanges stand to capture a much bigger portion of that activity. The potential losers? Dealers such as Goldman Sachs (GS) that have done a lot of swaps business. Standing at the back of the room, Chris Giancarlo, chair of the Wholesale Markets Brokers’ Association, likened the fight over swaps and futures to “the Maginot Line for the exchanges.”
Easley, de Prado, & O’Hara, SSRN, The Volume Clock: Insights into the High Frequency Paradigm, here. 2 LFT structural weaknesses
Over the last two centuries, technological advantages have allowed some traders to be faster than others. We argue that, contrary to popular perception, speed is not the defining characteristic that sets High Frequency Trading (HFT) apart. HFT is the natural evolution of a new trading paradigm that is characterized by strategic decisions made in a volume-clock metric. Even if the speed advantage disappears, HFT will evolve to continue exploiting Low Frequency Trading’s (LFT) structural weaknesses. However, LFT practitioners are not defenseless against HFT players, and we offer options that can help them survive and adapt to this new environment.
Nerval’s Lobster, Mars Rover Curiosity: Less Brain Power Than Apple’s iPhone 5, here. 3. So, remember that 8 hour to 238 second 2011 award winning Credit valuation and risk computation on the million dollar FPGA supercomputer with the Dataflow acceleration? That’s the Apollo Creed here, on a good day. There are days, (e.g., July 27, 2018 57.6 million km distance between Mars and Earth) when you can send the entire credit portfolio to Mars, compute the entire Risk and Valuation for the portfolio in the down time on the spare computer in the Mars Rover, then send the results back to Earth, and finish in ~360 seconds. That’s just about 50% slower than the 2011 award winning Credit valuation and risk computation on the million dollar FPGA supercomputer with the Dataflow acceleration. So, the message here is, I guess, if your computing infrastructure is on Mars … and has less brain power than an iPhone5 … then you are probably not going to be at the very top of the USD fixed/float Vanilla Swap League tables … on most days, but …if you own an iPhone5 here on earth … you have more brain power … than the 2011 award winning Credit valuation and risk computation on the million dollar FPGA supercomputer with the Dataflow acceleration?
“To give the Mars Rover Curiosity the brains she needs to operate took 5 million lines of code. And while the Mars Science Laboratory team froze the code a year before the roaming laboratory landed on August 5, they kept sending software updates to the spacecraft during its 253-day, 352 million-mile flight. In its belly, Curiosity has two computers, a primary and a backup. Fun fact: Apple’s iPhone 5 has more processing power than this one-eyed explorer. ‘You’re carrying more processing power in your pocket than Curiosity,’ Ben Cichy, chief flight software engineer, told an audience at this year’s MacWorld.”
Michael Feldman, HPCWire, Intel Weaves Strategy To Put Interconnect Fabrics On Chip, here. Boom goes the RDMA connection. All the Pluto Switch has to guarantee is that the packets get delivered in the same order as originally sent. The interleaving of the serial streams is important but probably not a huge deal.
Making the interconnect logic a first-class citizen on the processor, rather than just an I/O device would be a huge paradigm shift for the server market. If successfully executed at Intel, other chip vendors will be forced to follow suit. (AMD is likely already conjuring up something similar with the fabric technology it acquired from SeaMicro.) Meanwhile makers of discrete NICs and host adapter silicon will have to rethink their strategy, perhaps allying themselves with other chipmakers to offer competitive products.
Bill Dally, EE Times, Q&A: Nvidia’s Dally on 3-D ICs, China, cloud computing, here. More complete interview reporting that HPC Wire recently summarized. EE Times may make you register for this but it is otherwise free. On China’s microprocessors:
Five years ago Godson was laughable. Now it’s competent but not state of the art. If they continue, I would expect them to be matching the West in three to five years and then pulling ahead. Quite frankly, this country is not investing as much in R&D in these strategic areas. It’s a question of government investment in research. In computing it’s slowed to a trickle.
If we want to have a pipeline of innovations that can fuel competitive products going forward, the government needs to invest in stuff beyond the horizon of what companies will reasonably invest in. The fundamental research lifts all the boats.
IB Times, ARM, Intel Battle Heats Up, here. Microprocessor server HPC is a side show, w Intel holding 94+% share.
Low-power processor maker ARM Holdings PLC (Nasdaq: ARMH) is stepping up the rhetoric against chip rival Intel Corp. (Nasdaq: INTC), saying it expects to take more of Intel‘s share in the notebook personal-computer market than Intel can take from it in the smartphone market.
I notice that Emanuel Derman is about to release his new book. The tome seems to deal with how the failings of finance theory can impact the world. This sounds very close to what my Lecturing Birds attempted to do. There are big differences though.
For one, Derman knows much more than I do about the subject matter.
He is also a better writer.
But I suspect that there is an area where I may have a slight comparative advantage. I am an amateur, a dilettante, a stranger in a strange land. Derman is a pro in the field. While he is way more open and honest than most other pros in this debate, he may not want to be more open and honest than necessary. In other words, he probably can´t or doesn´t want to be a denunciator. He can´t or doesn´t want to be too critical or too cynical. I, on the other hand, was able to be stringently accusatorial because I had no allegiance but to the evidence I unearthed and what such findings dictated me to conclude. Derman can highlight VaR´s weaknesses but he might not want to call for its banning. Derman can talk about BSM´s flaws, but he might not want to embrace Taleb-Haug. Derman can denounce the unrealism of models but he might not want to lead a campaign against the (possibly impractical, probably lethal) modelling of finance.
My Little Pony Physics, You Tube, here. Going viral via Tosh.0.
Weisenthal, Business Insider,Everyone Agrees: The ECB Is About To Make The Biggest Decision In Its History, here.
All the politicians in Greece (even the mainstream ones) have said they want to renegotiate the bailout agreement.
If the rest of Europe doesn’t back down and agree to this, then the ECB will have to make a huge decision.
Unless Greece chooses to leave the Euro area, which we doubt will happen, a Greek exit will require the rest of the region to push the country out. The mechanism for this will be the ECB excluding the Greek central bank from TARGET2, the regional payments and settlement system. Although this might look like a technical decision about monetary plumbing, the ECB will elevate this to the Euro area heads of state. It will be the most important political decision since EMU’s launch.
HPC Wire, Intel Rolls Out New Server CPUs, here.
Since the E5-4600 supports the Advanced Vector Extensions (AVX), courtesy of the Sandy Bridge microarchitecture, the new chip can do floating point operations at twice the clip of its pre-AVX predecessors. According to Intel, a four-socket server outfitted with E5-4650 CPUs can deliver 602 gigaflops on Linpack, which is nearly twice the flops that can be achieved with the top-of the-line E7 technology. That makes this chip a fairly obvious replacement for the E7 when the application domain is scientific computing.
Extreme Tech, Ivy Bridge: Intel’s killing blow on AMD, here. Let’s look at this again. For the FinQuant application space I’d estimate somewhere between 50% and 85% of what you care about in selecting a Linux server is the current, expected future, and realized future feature size of the fab producing the server’s microprocessors and chips. There are lots of other important variables: system and microprocessor architecture, programming languages, network transmission lines, compilers, operating systems, file systems, databases, etc. and each alone can make or break a FinQuant app, but they are all tails. The microprocessor fab feature size is the dog, it effectively determines how well my FinQuant infrastructure scales with Moore’s Law. The comparative technology priority has not always been this way. There used to be different instruction set architectures, networks were slower than DRAMs, and memories were small all requiring evaluation in addition to the shrinking microprocessor fab feature size. In all likelihood the comparative technology priorities will change in the future as well.
Right now, Intel Sandy Bridge is 32nm, Ivy Bridge is 22nm, AMD Operton is 28nm, Xilinx is 28nm, Achronix is 22nm and the microprocessor market share main event is between AMD and Intel over design wins in mobile systems. Server-side Intel holds 95% market share to AMD 5%. Intel tries to set expectations of 22nm by 2013 and 14nm by 2014, here for example while showing the Chandler, Ariz 14 nm fab construction, here. Recall that things do not always move so smoothly for Intel, think about the relatively recent 8M Sandy Bridge support chip recall and Itanium. On the other hand AMD’s problems appear to be a shade worse than Intel’s witness: ars technica on Server market share here, The Register here, Extreme Tech here. I don’t know how much these websites are owned or comped by Intel, but if i am holding a bunch of Opteron server-side exposure it is probably safe to argue that it’s time to think about a hedge.
All things being equal, if I am aggressively setting up an HPC FinQuant infrastructure play now. I kind of want to be production ready with 22 nm silicon by the end of 2012 looking to set up a smooth infrastructure transition to 14nm in 2014.
Anand Tech, Intel’s Ivy Bridge Architecture Exposed, here. Not sure how much I care about the integrated GPU for server side FinQuant apps unless the AVX2 is somehow related to the GPU.
ars, Transactional memory going mainstream with Intel Haswell, here.
phoronix, Compilers Mature For Intel Sandy/Ivy Bridge, Prep For Haswell, here. Wow Treasure.
tom’s hardware, AMD Steals Market Share From Intel, here. The interesting fight is in mobile from the market’s perspective. Servers not so interesting.
Xilinx, High Performance Computing Using FPGAs, Sep 2010, here.
The shift to multicore CPUs forces application developers to adopt a parallel programming model to exploit CPU performance. Even using the newest multicore architectures, it is unclear whether the performance growth expected by the HPC end user can be delivered, especially when running the most data- and compute- intensive applications. CPU-based systems augmented with hardware accelerators as co-processors are emerging as an alternative to CPU-only systems. This has opened up opportunities for accelerators like Graphics Processing Units (GPUs), FPGAs, and other accelerator technologies to advance HPC to previously unattainable performance levels.
I buy the argument to a degree. As the number of cores per chip grow, the easy pipelining and parallelization opportunities will diminish. The argument is stronger if there are more cores per chip. 8 cores or under per general purpose chip it’s sort of a futuristic theoretical argument. More than a few programmers can figure out how to code up a 4 to 8 stage pipeline for their application without massive automated assistance. But the FPGA opportunity does exist.
The convergence of storage and Ethernet networking is driving the adoption of 40G and 100G Ethernet in data centers. Traditionally, data is brought into the processor memory space via a PCIe network interface card. However, there is a mismatch of bandwidth between PCIe (x8, Gen3) versus the Ethernet 40G and 100G protocols; with this bandwidth mismatch, PCIe (x8, Gen3) NICs cannot support Ethernet 40G and 100G protocols. This mismatch creates the opportunity for the QPI protocol to be used in networking systems. This adoption of QPI in networking and storage is in addition to HPC.
I buy the FPGA application in the NIC space. I want my NIC to go directly to L3 pinned pages, yessir I do, 100G please.
Xilinx FPGAs double their device density from one generation to the next. Peak performance of FPGAs and processors can be estimated to show the impact of doubling the performance on FPGAs [Ref 6], [Ref 7]. This doubling of capacity directly results in increased FPGA compute capabilities.
The idea proposed here is that you want to be on the exponentially increasing density curve for the FPGAs in lieu of clock speed increases you are never going to see again. Sort of a complicated bet to make for mortals, maybe.
I like how they do the comparisons though. They say here is our Virtex-n basketball player and here is the best NBA Basketball player … and they show you crusty old Mike Bibby 2012. Then they say watch as the Virtex-n basketball player takes Mike Bibby down low in the post, and notice the Virtex-n basketball player is still growing exponentially. So you can imagine how much better he will do against Mike Bibby in the post next year. Finally they say that Mike Bibby was chosen as the best NBA player for this comparison by his father Henry, who was also a great NBA player.
FPGAs tend to consume power in tens of watts, compared to other multicores and GPUs that tend to consume power in hundreds of watts. One primary reason for lower power consumption in FPGAs is that the applications typically operate between 100–300 MHz on FPGAs compared to applications on high-performance processors executing between 2–3 GHz.
Silly making Lemonade out of Lemons argument, the minute I can have my FPGAs clocked at 3 GHz I throw away the 300MHz FPGAs, no?
Intel, An Introduction to the Intel QuickPath Interconnect, QPI, Jan 2009, here.
Xilinx Research Labs/NCSA, FPGA HPC – The road beyond processors, Jul 2007, here. Need more current references but I keep hearing the same themes in arguments for FGPA HPC, so let’s think about this for a bit:
FPGAs have an opening because you are not getting any more clocks from microprocessor fab shrinks: OK.
Power density: meh. Lots of FinQuant code can run on a handful of cores. The Low Latency HFT folks cannot really afford many L2 misses. The NSA boys are talking about supercomputers for crypto not binary protocol parsing.
Microprocessors have all functions that are hardened in silicon and you pay for them whether you use them or not and you can’t use that silicon for something else: Meh, don’t really care if I use all the silicon on my 300 USD microprocessor as long as the code is running close to optimal on the parts of the silicon useful to my application. It would be nice if I got more runtime performance for my 300USD, no doubt. This point is like Advil is bad because you don’t always need to finish the bottle after you blow out your ankle. Yeah, I understand the silicon real estate is the most expensive in the world.
Benchmarks: Black Scholes 18msec FPGA @ 110 Mhz Virtex-4 203x faster than Opeteron – 2.2 Ghz: You Cannot be Serious! 3.7 microseconds per Black Scholes evaluation was competitive performance at the turn of the century. The relative speedup slides and quotations make me nervous. Oh, Celoxica provided the data – hey Black Scholes in 36 Nanoseconds on a single core of a dual core off-the-shelf general microprocessor from 2007. So the Virtex-4 does 1M Black Scholes evaluations in 18 milliseconds flat to competitive code on a dual core general purpose off-the-shelf microprocessor in 2007.
Make it easy for the users to use this hardware and get „enough of a performance‟ increase to be useful: meh, it’s for applications that do not need to go fast, for now (2007)?
Do not try to be the fastest thing around when being as fast with less power is sufficient: meh, really do not care so much about the power thing
FPGA: Different operations map to different silicon allows massive pipelining; lots of parallelism: OK. So, why bother with the previous two points?
Eggers/ U. Washington, CHiMPS, here. Eggers is reasonable.
There have been (at least) two hindrances to the widespread adoption of FPGAs by scientific application developers: having to code in a hardware description language, such as Verilog (with its accompanying hardware-based programming model) and poor FPGA memory performance for random memory accesses. CHiMPS, our C-to-FPGA synthesis compiler, solves both problems with one memory architecture, the many-cache memory model.
Many-cache organizes the small, distributed memories on an FPGA into application-specific caches, each targeting a particular data structure or region of memory in an application and each customized for the particular memory operations that access it.
CHiMPS provides all the traditional benefits we expect from caching. To reduce cache latency, CHiMPS duplicates the caches, so that they’re physically located near the hardware logic blocks that access them. To increase memory bandwidth, CHiMPS banks the caches to match the memory parallelism in the code. To increase task-level parallelism, CHiMPS duplicates caches (and their computation blocks) through loop unrolling and tiling. Despite the lack of FPGA support for cache coherency, CHiMPS facilitates data sharing among FPGA caches and between the FPGA and its CPU through a simple flushing of cached values. And in addition, to harness the potential of the massively parallel computation offered by FPGAs, CHiMPS compiles to a spatial dataflow execution model, and then provides a mechanism to order dependent memory operations to retain C memory ordering semantics.
CHiMPS’s compiler analyses automatically generate the caches from C source. The solution allows scientific programmers to retain their familiar programming environment and memory model, and at the same time provides performance that is on average 7.8x greater and power that is one fourth that of a CPU executing the same source code. The CHiMPS work has been published in the International Symposium on Computer Architecture (ISCA, 2009), the International Conference on Field Programmable Logic and Applications (FPL, 2008), and High-Performance Reconfigurable Computing Technology and Applications (HPRCTA, 2008), where it received the Best Paper Award.
Intel, Intel’s Revolutionary 22 nm Transistor Technology, Mark Bohr and Kaizad Mistry, May 2011, here.
EE Times, Intel exec says fabless model ‘collapsing’, here. Bohr is the guy from the 22nm presentation (above).
It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intel’s archrival AMD.
But Bohr stretches the point too far when he says the foundries and fabless companies won’t be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors won’t be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
Anand Tech, Ivy Bridge posts, here. Motherboard and laptop implementation commentary.
Intel, Haswell New Instruction Description Now Available, June 2011, here.
Intel just released public details on the next generation of the x86 architecture. Arriving first in our 2013 Intel microarchitecture codename “Haswell”, the new instructions accelerate a broad category of applications and usage models. Download the full Intel® Advanced Vector Extensions Programming Reference (319433-011).
These build upon the instructions coming in Intel® microarchitecture code name Ivy Bridge, including the digital random number generator, half-float (float16) accelerators, and extend the Intel® Advanced Vector extensions (Intel® AVX) that launched in 2011.
AVX2 integer data types expanded to 256-bit SIMD; Bit manipulation instructions; Gather; Any-to-Any permutes; Vector-Vector shifts; Floating point Multiply Accumulate.
SD Times, Fog Around Intel Compilers, here.
Agner Fog is a computer science professor at the University of Copenhagen‘s college of engineering. As he puts it, “I have done research on microprocessors and optimized code for more than 12 years. My motivation is to make code compatible, especially when it pretends to be.”
Fog has written a number of blog entries about Intel’s compilers and how they treat competing processors. In November, AMD and Intel settled, and Fog has written up a magnificent analysis of the agreement.
If you have any interest in compilers, and in Intel’s compilers, you should definitely read his paragraph-by-paragraph read through.
Fog, Agner, Software Optimization Resources, here. I was reading Fog’s Optimizing Software in C++ (here) this morning. It’s a runtime optimization guide for Windows, Linux, and Mac. I have seen it before and perhaps been remiss in not commenting more fully. Without the benefit of trying out many of Fog’s code samples and directives against current versions of ICC and GCC I cannot be certain, but based on what I have optimized in the recent past, his body of works looks very legitimate and exhaustive. You ask, how exhaustive? Let’s start with the copyright, it’s got a succession plan:
This series of five manuals is copyrighted by Agner Fog. Public distribution and mirroring is not allowed. Non-public distribution to a limited audience for educational purposes is allowed. The code examples in these manuals can be used without restrictions. A GNU Free Documentation License shall automatically come into force when I die. See http://www.gnu.org/copyleft/fdl.html.
Professor Fog is laying out code optimization paths for 4 different compilers on 3 different operating systems. I will not and cannot check out/verify all the scenarios presented because I possess the attention span of a squirrel compared to Professor Fog. He also provides a page on random number generators, here, which seems legit to the extent that he points you to Matsumoto’s Mersenne Twister RNG page, here. The random number references do not appear to be as comprehensive as the C++ runtime optimization references. But this looks to be a case of:
in a most complimentary way to Professor Fog.
Crooked Timber, Harvard Library pushes open access, here.
We write to communicate an untenable situation facing the Harvard Library. … The Faculty Advisory Council to the Library, representing university faculty in all schools and in consultation with the Harvard Library leadership, reached this conclusion: major periodical subscriptions, especially to electronic journals published by historically key providers, cannot be sustained: continuing these subscriptions on their current footing is financially untenable. … It is untenable for contracts with at least two major providers to continue on the basis identical with past agreements. Costs are now prohibitive. … since faculty and graduate students are chief users, please consider the following options open to faculty and students (F) and the Library (L), state other options you think viable, and communicate your views:
Make sure that all of your own papers are accessible by submitting them to DASH in accordance with the faculty-initiated open-access policies (F). Consider submitting articles to open-access journals, or to ones that have reasonable, sustainable subscription costs; move prestige to open access (F). If on the editorial board of a journal involved, determine if it can be published as open access material, or independently from publishers that practice pricing described above. If not, consider resigning (F).
Extreme Tech, Intel Core i7-3770K review: Ivy Bridge brings lower power, better performance, here.
Intel’s Ivy Bridge (IVB) has been one of the hottest tech topics of the past 12 months — we haven’t seen this much interest in a CPU since Intel launched Nehalem. Ivy Bridge is the first 22nm processor at a time when die shrinks have become increasingly difficult, the first CPU to use FinFETs (Intel calls its specific implementation Tri-Gate), and it’s a major component of Intel’s ultrabook initiative. If all goes well, Ivy Bridge will usher in a new series of 15W ultra-mobile parts, though these won’t reach the market for a little while yet.
Ivy Bridge is a “tick” in Intel’s tick-tock model, but the company is referring to its latest architecture as a “tick+.” The reason for the change is the disparity of improvement between Ivy Bridge’s CPU and GPU components. IVB’s CPU core is a die-shrunk Sandy Bridge (SNB) with a few ultra-low-level efficiency improvements. Performance improvements on the CPU side are in the 5-10% range. Unlike Westmere (Nehalem’s “tick”), which offered 50% more cores, Ivy Bridge keeps Sandy Bridge’s quad-core configuration.
The FPGA folks get an opening in HPC floating point if they can get more aggressive on clock speed and not worry so much about power efficiency, while Intel tries to shake out AMD mobile CPU market share with the Ivy Bridge integrated GPU. I see the Maxeler bet on adding parallelism through Dataflow architecture as interesting/plausible – but nowhere near a done deal at this point.
Liquid Nitrogen Overclocking, The Fastest Rack Mounted Servers in the World, here. Running Intel i7-2700K at 5GHz.
Financial Sense: SPY versus SPX, here. SPX historical data doesn’t account for dividends while SPY does. Chris Whalen interview, The Fallacy of “Too Big To Fail”–Why the Big Banks Will Eventually Break Up, here.
IEEE Transactions on Computers, Ferrer et.al., Progressive Congestion Management Based on Packet Marking and Validation Techniques, here.
Business Insider, HSBC’s Incredible Video On The Rise Of Correlated Markets, here. The rolling time window is pretty good.
ExtremeTech, What can you do with a supercomputer? here. I think there may be a stronger result in here. If you are not doing Weather Forecasting, Nuke simulations, Crypto, Airplane Design, or Molecular Dynamics simulation the thing you are computing on probably is not a supercomputer. If you need to discount cashflows off a curve, even if they are contingent cashflows, and your programmers tell you they need a supercomputer here’s what you do. Ask the programmers if they are doing: Weather Forecasting, Nuke simulations, Crypto, Airplane Design, or Molecular Dynamics if the answer is no, you do not need a supercomputer. If the answer is yes, the problem that you have is bigger than any supercomputer is going to address in 2012.
London Whale: DealBreaker, JPMorgan’s Voldemort Probably Isn’t That Magical, here; and More Voldemort v. Volker, here. Salmon, Bruno Iksil and the CHIPS trade, here. Pollack/Alphaville, Thar she blows! here. Big market moving off-the-run index (series 9 HG CDX on-the-run when the Credit Crisis hit) trades by one of only a handful of US Corporate Loan sources is going to attract attention. Folks need to process the idea that the information distribution could be even more asymmetric than in the past (even with Volker in place) e.g., default risk in the CDS market maybe less than commonly expected if your US Corporate Loan folks are standing by to offer credit to the distressed. From Pollack:
Typically the most liquid tenors for credit indices are the 5-year and the 10-year. The 5-year contract for the CDX.NA.IG.9 will mature in December 2012, the 10-year in December 2017. This index is no spring chicken.
So why the recent increase in volume?
There are some perfectly logical reasons for the 9s to have high volume in general, so the first part of the above chart makes sense to us. This is because it was the last pre-full-blown-crisis index. It became awash in liquidity at the time by virtue of being the on-the-run index, and then the world came crashing down around it. Subsequent indices didn’t find their feet in the same way.
The 9s were used to build structured products; they were used to hedge other more customised structured products; and so on. It also had the last active set of tranches traded with reference to it. All of which leads us to think that a large amount of net notional for this index relative to others isn’t that weird.
But then… it increased like crazy in January of this year, and that’s the weird part. What went on in 2012? A whale swam in…?
At some point we are going to get a glimpse into how the Maxeler FPGA implementation of the Gaussian Copula for the JPM Credit batch fits into this story. Doubt that the $100bn notional CDX positions are marked against anything other than the standard default swap model with some specially quoted spreads. If there is something going on in series 9 tranches though then maybe you do optimize the Gaussian Copula code to run on a
Mac Pro in 20FPGA Supercomputer + 1000 grid nodes in 238 seconds.
Success in high-performance computing (HPC) is often difficult to measure. Ultimately it depends on your goals and budget. Many casual practitioners assume that a good HPL (High Performance Linpack) benchmark and a few aisles of servers demonstrate a successful HPC installation. However, this notion could not be further from the truth, unless your goal is to build a multimillion dollar HPL machine. In reality, a successful and productive HPC effort requires serious planning and design before purchasing hardware. Indeed, the entire process requires integration skills that often extend far beyond those of a typical data center administrator.
The multivendor nature of today’s HPC market necessitates that the practitioner make many key decisions. In this paper, I outline several common pitfalls and how they might be avoided.
US Regulations: NYT/DealBook, Regulators to Ease a Rule on Derivatives Dealers, here; Business Insider, ANDREW LO: Thanks To The JOBS Act, Hedge Funds Will Be Able To Use Ads To Trick Prospective Investors, here; Huff Post, SEC Fails To Monitor More Than Half Of Stock Trading, Former Agency Lawyers Say, here.
I’m a former high frequency trader. And following the tradition of G.H. Hardy, I feel the need to make an apology for my former profession. Not an apology in the sense of a request for forgiveness of wrongs performed, but merely an intellectual justification of a field which is often misunderstood.
In this blog post, I’ll attempt to explain the basics of how high frequency trading works and why traders attempt to improve their latency. In future blog posts, I’ll attempt to justify the social value of HFT (under some circumstances), and describe other circumstances under which it is not very useful. Eventually I’ll even put forward a policy prescription which I believe could cause HFT to focus primarily on socially valuable activities.