io9, Wikipedia’s founder will help make academic research available to all, Wow, Gowers is doing good. But it looks like  Jimmy Wales is going to get to do the historic Berlin “Tear down this paywall” speech. Hope the ACM and IEEE archives open up soon.

Microprocessor Report, website, here. Haven’t seen this in a long while. Used to be fabulous for general purpose HPC stuff. Not sure how much of a player it is these days. Seems to be mostly locked behind paywall.

Tom’s Hardware, Leaked Slide Shows Intel Haswell Set for March-June 2013, here.

Intel is set to launch its new Ivy Bridge processor in April 2012 and will make the move to 22 nm on LGA 1155. It will feature faster integrated graphics controller, lower TDP, higher clock speeds and overclocking ceiling with the 22 nm process. Right around the corner, Intel is set to release its “tock” strategy with the Ivy Bridge successor, codename Haswell.

and

Haswell is expected to have Advanced Vector Extensions 2 (AVX2), DX11.1, OpenGL 3.2, Thunderbolt, Transactional Synchronization Extensions (TSX) and Windows 8 support.

It’s the AVX2 and possibly the Transactional Synchronization Extensions you are willing to think hard about from the FinQuant app side. For example, I think w. AVX2 there is mumbling about giving you 8-way SIMD scatter-gather. Think of that as single clock binary protocol parsing, after everything is aligned and suitable genuflecting has taken place with the compiler switches. Most of the other headline stuff seems to be there to do a bunch of SoC stuff to fight for mobile systems market share.

Low Latency, New Packet Processor from GE Delivers the Outstanding Performance Demanded by Communications Companies and the High Frequency Trading (HFT) Market, here. NYT Cavium, Inc , here.

HPC Wire, Myricom Claims Lowest UDP, TCP Latency for High Frequency Trading, here.

Myricom DBL 2.0 software has benchmarked application-to-application UDP latency of under 3.5 microseconds and transparent sockets TCP latency of 4.0 microseconds. For HFT applications, DBL enables unmatched networking performance for UDP multicast and TCP order execution, all over industry-standard 10-Gigabit Ethernet.

So, we’re getting expectations set at 3 to 4 microseconds for kernel bypass.  Which in turn will presumably be overtaken by RDMA NIC to L3, or will it still cost me multiple microseconds to traverse the TCP stack for ECC, retransmission, and packet ordering?

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